Digital Electronics BTEC-404 Sept 2020 PTU B.Tech EE Paper

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B.Tech. (EE-2011 Batch)

DIGITAL ELECTRONICS 

Subject Code : BTEE-404          M.Code : 57103

Time : 2 Hrs.                          Max. Marks : 30

INSTRUCTIONS TO CANDIDATES :
1. Attempt any FIVE question(s), each question carries 6 marks.

Digital Electronics BTEE-404 5th Sem Batch 2011 Onwards B.Tech PTU Sept 2020 Paper

SECTION-A

1. Design a 4 bit odd parity generator. At the receiver end, the detected code is 10011. What
are the conditions in which this code is received with error?
2. Minimize the following expression using K-MAP
F = Σm (0,2,3,5,8,10,13,15,18,22,23,24, 27) + d (7, 11, 21, 29, 30)
3. Design the circuit diagram of CMOS for the following expression
F = A’B+ CD’
4. Implement the logic function F = Σm (1, 2, 3, 5, 7) using 8:1, 4:1 and 2:1 Multiplexers.
5. Draw the internal structure of D to SR Flip flop conversion. Also show the timing
specifications of the flip flop.
6. Design MOD 7 asynchronous counter and draw the timing diagrams.
7. Write a VHDL code for 2 bit comparator.
8. How many bits are required for a DAC for 12.6 V full scale output and 20 mV resolution?

Digital Electronics BTEE-404 4th Sem Batch 2011 Onwards B.Tech PTU Sept 2020 Paper

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Section a Digital Electronics BTEE-404 4th Sem B.Tech PTU Sept 2020 Paper

Design a 4 bit odd parity generator. At the receiver end, the detected code is 10011. What are the conditions in which this code is received with error?

Design a 4 bit odd parity generator. At the receiver end, the detected code is 10011. What are the conditions in which this code is received with error?

Minimize the following expression using K-MAP F = Σm (0,2,3,5,8,10,13,15,18,22,23,24, 27) + d (7, 11, 21, 29, 30)

Minimize the following expression using K-MAP
F = Σm (0,2,3,5,8,10,13,15,18,22,23,24, 27) + d (7, 11, 21, 29, 30)

Design the circuit diagram of CMOS for the following expression F = A’B+ CD’

Design the circuit diagram of CMOS for the following expression
F = A’B+ CD’

Implement the logic function F = Σm (1, 2, 3, 5, 7) using 8:1, 4:1 and 2:1 Multiplexers

Implement the logic function F = Σm (1, 2, 3, 5, 7) using 8:1, 4:1 and 2:1 Multiplexers.

Draw the internal structure of D to SR Flip flop conversion. Also show the timing specifications of the flip flop.

Draw the internal structure of D to SR Flip flop conversion. Also show the timing
specifications of the flip flop.

Design MOD 7 asynchronous counter and draw the timing diagrams.

Design MOD 7 asynchronous counter and draw the timing diagrams.

Write a VHDL code for 2 bit comparator.

Write a VHDL code for 2 bit comparator.

How many bits are required for a DAC for 12.6 V full scale output and 20 mV resolution?

How many bits are required for a DAC for 12.6 V full scale output and 20 mV resolution?

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